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| A3941 Automotive Full Bridge MOSFET Driver Features and Benefits High current gate drive for N-channel MOSFET full bridge High-side or low-side PWM switching Charge pump for low supply voltage operation Top-off charge pump for 100% PWM Cross-conduction protection with adjustable dead time 5.5 to 50 V supply voltage range Integrated 5 V regulator Diagnostics output Low current sleep mode Description The A3941 is a full-bridge controller for use with external N-channel power MOSFETs and is specifically designed for automotive applications with high-power inductive loads, such as brush DC motors. A unique charge pump regulator provides full (>10 V) gate drive for battery voltages down to 7 V and allows the A3941 to operate with a reduced gate drive, down to 5.5 V. A bootstrap capacitor is used to provide the above-battery supply voltage required for N-channel MOSFETs. An internal charge pump for the high-side drive allows DC (100% duty cycle) operation. The full bridge can be driven in fast or slow decay modes using diode or synchronous rectification. In the slow decay mode, current recirculation can be through the high-side or the lowside FETs. The power FETs are protected from shoot-through by resistor adjustable dead time. Integrated diagnostics provide indication of undervoltage, overtemperature, and power bridge faults, and can be configured to protect the power MOSFETs under most short circuit conditions. The A3941 is supplied in a 28-pin TSSOP power package with an exposed thermal pad (suffix LP). This package is lead (Pb) free, with 100% matte-tin leadframe plating. Package: 28-pin TSSOP with exposed thermal pad (suffix LP) Not to scale Typical Application VBAT PWM Direction A3941 Fault Flags 3941-DS, Rev. 2 A3941 Automotive Full Bridge MOSFET Driver Selection Guide Part Number A3941KLP-T A3941KLPTR-T Packing 50 pieces per tube 4000 pieces per reel Absolute Maximum Ratings* Characteristic Load Supply Voltage Logic Inputs and Outputs V5 Pin LSS Pin VDSTH Pin SA and SB Pins VDRAIN Pin GHA and GHB Pins GLA and GLB Pins CA and CB Pins Operating Temperature Range Junction Temperature Transient Junction Temperature Storage Temperature Range ESD Rating, Human Body Model ESD Rating, Charged Device Model *With respect to GND. TA TJ(max) TtJ Tstg AEC-Q100-002, all pins AEC-Q100-011, all pins Overtemperature event not exceeding 1 s, lifetime duration not exceeding 10 hr; guaranteed by design characterization Range K Symbol VBB Notes Rating -0.3 to 50 -0.3 to 6.5 -0.3 to 7 -4 to 6.5 -0.3 to 6.5 -5 to 55 -5 to 55 Sx to Sx+15 -5 to 16 -0.3 to Sx+15 -40 to 150 150 175 -55 to 150 2000 1050 Units V V V V V V V V V V C C C C V V THERMAL CHARACTERISTICS may require derating at maximum conditions Characteristic Package Thermal Resistance Symbol RJA RJP *Additional thermal information available on Allegro website. Test Conditions* 4-layer PCB based on JEDEC standard 2-layer PCB with 3.8 in.2 of copper area each side Value 28 32 2 Units C/W C/W C/W Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 2 A3941 Automotive Full Bridge MOSFET Driver Functional Block Diagram Battery + CP VBB CP2 CP1 Charge Pump Regulator VBAT VREG CREG V5 +5V Reg FF1 FF2 VDSTH Diagnostics and Protection Charge Pump Bootstrap Monitor VDRAIN CA GHA CBOOTA High Side RGHA SA RGHB PWMH PWML Low Side GLA RGLA LSS RGLB Control Logic PHASE Charge Pump Bootstrap Monitor CB CBOOTB SR High Side GHB SB RESET Low Side LSS RDEAD GND PAD GLB Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 3 A3941 Automotive Full Bridge MOSFET Driver ELECTRICAL CHARACTERISTICS valid at TJ = -40C to 150C, VBB = 7 to 50 V, unless noted otherwise Characteristics Supply and Reference Load Supply Voltage Functional Operating Range1 Load Supply Quiescent Current VBB IBBQ IBBS RESET = high, outputs = low, VBB = 12 V RESET = low, Sleep mode, VBB = 12 V VBB > 9 V, IREG = 0 to 10 mA 7.5 V < VBB 9 V, IREG = 0 to 7 mA VREG Output Voltage VREG 6 V < VBB 7.5 V, IREG = 0 to 7 mA 5.5 V < VBB 6 V, IREG < 5.5 mA V5 Output Voltage V5 Line Regulation V5 Load Regulation V5 Short-Circuit Current Bootstrap Diode Forward Voltage Bootstrap Diode Resistance Bootstrap Diode Current Limit Top-off Charge Pump Current Limit High-Side Gate Drive Static Load Resistance V5(out) V5(line) V5(load) I5M VfBOOT rD IDBOOT ITOCPM RGSH tr tf RDS(on)UP RDS(on)DN VGHX VGLX tP(off) tP(on) tPP tOO Input change to unloaded gate output change Input change to unloaded gate output change Measured between corresponding transition points on both phases Measured across one phase RDEAD = 3 k Dead Time2 tDEAD RDEAD = 30 k RDEAD = 240 k RDEAD tied to V5 CLOAD = 1 nF, 20% to 80% CLOAD = 1 nF, 80% to 20% TJ = 25C, IGHx = -150 mA TJ = 150C, IGHx = -150 mA TJ = 25C, IGLx = 150 mA TJ = 150C, IGLx = 150 mA Bootstrap capacitor fully charged No load I5 = -2 mA I5 = 0 to -2 mA VBB = 40 V, V5 = 0 V ID = 10 mA ID = 100 mA rD(100mA) = (VfBOOT(150mA) - VfBOOT(50mA)) / 100 mA 5.5 - - 12.5 12.5 2xVBB - 2.5 8.5 4.5 - - - 0.4 1.5 6 250 - 250 - - 6 10 2 3 VCx - 0.2 VREG - 0.2 60 60 - - - 815 - - - 10 - 13 13 - 9.5 5 15 50 28 0.7 2.2 10 500 400 - 35 20 8 13 3 4.5 - - 90 90 10 10 180 960 3.5 6 50 14 10 13.75 13.75 - - 5.5 40 100 30 1.0 2.8 20 750 - - - - 12 16 4 6 - - 150 150 - - - 1110 - - V mA A V V V V V mV mV mA V V mA A k ns ns V V ns ns ns ns ns ns s s Symbol Test Conditions Min. Typ. Max. Units Gate Output Drive Turn-On Time Turn-Off Time Pullup On Resistance Pulldown On Resistance GHx Output Voltage GLx Output Voltage Turn-Off Propagation Delay2 Turn-On Propagation Delay2 Propagation Delay Matching, Phase-to-Phase Propagation Delay Matching, On-to-Off Continued on the next page... Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 4 A3941 Automotive Full Bridge MOSFET Driver ELECTRICAL CHARACTERISTICS (continued) valid at TJ = -40C to 150C, VBB = 7 to 50 V, unless noted otherwise Characteristics Logic Inputs and Outputs FF1 and FF2 Fault Output (Open Drain) FF1 and FF2 Fault Output Leakage Current3 RDEAD Current3 Input Low Voltage Input High Voltage Input Hysteresis (Except RESET Pin) Input Hysteresis (RESET Pin) Input Current (Except RESET Pin)3 Input Pulldown Resistor (RESET Pin) RESET Pulse Time VFF(L) IFF(H) IDEAD VIN(L) VIN(H) VINhys VINRSThys IIN RPD tRES VREGUVon VREGUVoff VBOOTUV VBOOTUVhys V5UVoff V5UVhys VDSTH IDSTH VDSDIS VDRAIN IDRAIN VSTGO VSTBO TJF TJFhys 0 V < VDSTH < 2 V When not connected directly to V5 VDSTH = 2 V, VBB = 12 V, VDSTH = 2 V, VBB = 12 V, 0 V < VDRAIN < VBB High-side on, VDSTH 1 V High-side on, VDSTH < 1 V Low-side on, VDSTH 1 V Low-side on, VDSTH < 1 V Temperature increasing Recovery = TJF - TJFhys V5 falling VREG rising VREG falling Cx with respect to Sx 0 V < VIN < V5 IFF = 1 mA, fault not present VFF = 5 V, fault present RDEAD = GND - -1 -200 - 3.5 300 200 -1 - 0.1 7.5 6.75 59 - 3.4 300 0.1 - 4.95 7 - - -150 - -150 150 - - - - - - 500 - - 50 - 8 7.25 - 13 3.6 400 - 10 - VBB - 100 50 100 50 170 15 0.4 1 -70 1 - - - 1 - 3.5 8.5 7.75 69 - 3.8 500 2 30 - 50 250 - 150 - 150 - - V A A V V mV mV A k s V V %VREG %VREG V mV V A V V A mV mV mV mV C C Symbol Test Conditions Min. Typ. Max. Units Protection VREG Undervoltage Lockout Threshold Bootstrap Undervoltage Threshold Bootstrap Undervoltage Hysteresis V5 Undervoltage Turn-Off Threshold V5 Undervoltage Hysteresis VDSTH Input Range VDSTH Input Current VDSTH Disable Voltage VDRAIN Input Voltage VDRAIN Input Current Short-to-Ground Threshold Offset4 Short-to-Battery Threshold Offset5 Overtemperature Fault Flag Threshold Overtemperature Fault Hysteresis 1Functions correctly, but parameters are not guaranteed, below the general limits (7 V). 2See Gate Drive Timing diagrams. 3For input and output current specifications, negative current is defined as coming out of (sourcing) the specified device pin. 4As V Sx decreases, fault occurs if VBAT -VSx > VSTG. STG threshold, VSTG = VDSTH + VSTGO . 5As V Sx increases, fault occurs if VSx - VLSS > VSTB . STB threshold, VSTB = VDSTH+VSTBO . Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 5 A3941 Automotive Full Bridge MOSFET Driver Timing Diagrams PWMH PWML tDEAD GHx GLx tP(off) Synchronous Rectification tDEAD tP(off) xHI xLO tP(on) GHx GLx tP(off) xHI xLO GHx GLx tP(on) tP(off) Low-Side PWM High-Side PWM Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 6 A3941 Automotive Full Bridge MOSFET Driver Functional Description The A3941 is a full-bridge MOSFET driver (pre-driver) requiring a single unregulated supply of 7 to 50 V. It includes an integrated 5 V logic supply regulator. The four high current gate drives are capable of driving a wide range of N-channel power MOSFETs, and are configured as two high-side drives and two low-side drives. The A3941 provides all the necessary circuits to ensure that the gate-source voltage of both high-side and low-side external FETs are above 10 V, at supply voltages down to 7 V. For extreme battery voltage drop conditions, correct functional operation is guaranteed at supply voltages down to 5.5 V, but with a reduced gate drive voltage. The A3941 can be driven with a single PWM input from a microcontroller and can be configured for fast or slow decay. Fast decay can provide four-quadrant motor control, while slow decay is suitable for two-quadrant motor control or simple inductive loads. In slow decay, current recirculation can be through the high-side or the low-side MOSFETs. In either case, bridge efficiency can be enhanced by synchronous rectification. Crossconduction (shoot through) in the external bridge is avoided by an adjustable dead time. A low power sleep mode allows the A3941, the power bridge, and the load to remain connected to a vehicle battery supply without the need for an additional supply switch. The A3941 includes a number of protection features against undervoltage, overtemperature, and power bridge faults. Fault states enable responses by the device or by the external controller, depending on the fault condition and logic settings. Two fault flag outputs, FF1 and FF2, are provided to signal detected faults to an external controller. used by the internal logic circuits and must always be decoupled by at least a 100 nF capacitor between the V5 pin and GND. The 5 V regulator is disabled when RESET is held low. Gate Drives The A3941 is designed to drive external, low on-resistance, power N-channel MOSFETs. It supplies the large transient currents necessary to quickly charge and discharge the external FET gate capacitance in order to reduce dissipation in the external FET during switching. The charge and discharge rate can be controlled using an external resistor in series with the connection to the gate of the FET. Gate Drive Voltage Regulation The gate drives are powered by an internal regulator which limits the supply to the drives and therefore the maximum gate voltage. When the VBB supply is greater than about 16 V, the regulator is a simple linear regulator. Below 16 V, the regulated supply is maintained by a charge pump boost converter, which requires a pump capacitor connected between the CP1 and CP2 pins. This capacitor must have a minimum value of 220 nF, and is typically 470 nF. The regulated voltage, nominally 13 V, is available on the VREG pin. A sufficiently large storage capacitor must be connected to this pin to provide the transient charging current to the low-side drives and the bootstrap capacitors. Top-off Charge Pump An additional top-off charge pump is Power Supplies A single power supply connection is required to the VBB pin through a reverse voltage protection circuit. The supply should be decoupled with a ceramic capacitor connected close to the VBB and ground pins. The A3941 operates within specified parameters with a VBB supply from 7 to 50 V and functions correctly with a supply down to 5.5 V. This provides a very rugged solution for use in the harsh automotive environment. V5 Pin A 5 V low current supply for external pullup resistors is provided for each phase. The charge pumps allow the high-side drives to maintain the gate voltage on the external FETs indefinitely, ensuring so-called 100% PWM if required. This is a low current trickle charge pump, and is operated only after a high-side FET has been signaled to turn on. The floating high-side gate drive requires a small bias current (<20 A) to maintain the highlevel output. Without the top-off charge pump, this bias current would be drawn from the bootstrap capacitor through the Cx pin. The charge pump provides sufficient current to ensure that the bootstrap voltage and thereby the gate-source voltage is maintained at the necessary level. Note that the charge required for initial turn-on of the high-side gate is always supplied by the bootstrap capacitor. If the bootstrap capacitor becomes discharged, the top-off charge pump will not provide sufficient current to allow the FET to turn on. provided by an integrated 5 V regulator. This regulator is also Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 7 A3941 Automotive Full Bridge MOSFET Driver In some applications a safety resistor is added between the gate and source of each FET in the bridge. When a high-side FET is held in the on-state, the current through the associated high-side gate-source resistor (RGSH) is provided by the high-side drive and therefore appears as a static resistive load on the top-off charge pump. The minimum value of RGSH for which the top-off charge pump can provide current is shown in the Electrical Characteristics table. GLA and GLB Pins These are the low-side gate drive outputs for LSS Pin This is the low-side return path for discharge of the capacitance on the FET gates. It should be tied directly to the common sources of the low-side external FETs through an independent low impedance connection. RDEAD Pin This pin controls internal generation of dead time during FET switching. * When a resistor greater than 3 k is connected between RDEAD and AGND, cross-conduction is prevented by the gate drive circuits, which introduce a dead time, tDEAD , between switching one FET off and the complementary FET on. The dead time is derived from the resistor value connected between the RDEAD and AGND pins. * When RDEAD is connected directly to V5, cross-conduction is prevented by the gate drive circuits. In this case, tDEAD defaults to a value of 6 s typical. Logic Control Inputs Four low-voltage level digital inputs provide control for the gate drives. These logic inputs all have a nominal hysteresis of 500 mV to improve noise performance. They are used together to provide fast decay or slow decay with high-side or low-side recirculation. They also provide brake, coast, and sleep modes as defined in tables 1 and 2. PWMH and PWML Pins These inputs can be used to control the external N-channel MOSFETs. External resistors between the gate drive output and the gate connection to the FET (as close as possible to the FET) can be used to control the slew rate seen at the gate, thereby providing some control of the di/dt and dv/dt of the SA and SB outputs. GLx going high turns on the upper half of the drive, sourcing current to the gate of the low-side FET in the external power bridge, turning it on. GLx going low turns on the lower half of the drive, sinking current from the external FET gate circuit to the LSS pin, turning off the FET. SA and SB Pins Directly connected to the motor, these terminals sense the voltages switched across the load. These terminals are also connected to the negative side of the bootstrap capacitors and are the negative supply connections for the floating high-side drives. The discharge current from the high-side FET gate capacitance flows through these connections, which should have low impedance circuit connections to the FET bridge. GHA and GHB Pins These terminals are the high-side gate drive outputs for the external N-channel FETs. External resistors between the gate drive output and the gate connection to the FET (as close as possible to the FET) can be used to control the slew rate seen at the gate, thereby controlling the di/dt and dv/dt of the SA and SB outputs. GHx going high turns on the upper half of the drive, sourcing current to the gate of the high-side FET in the external motor-driving bridge, turning it on. GHx going low turns on the lower half of the drive, sinking current from the external FET gate circuit to the corresponding Sx pin, turning off the FET. CA and CB Pins These are the high-side connections for the current in the power bridge. PWMH provides high-side chopping and PWML provides low-side chopping. When used together they control the power bridge in fast decay mode. The PWM options are provided in table 2. * Setting PWMH low turns off active high-side drives. This provides high-side-chopped slow-decay PWM. * Setting PWML low turns off active low-side drives. This provides low-side-chopped slow-decay PWM. * PWMH and PWML may also be connected together and driven with a single PWM signal. This provides fast-decay PWM. PHASE Pin The state of the PHASE pin determines the positive bootstrap capacitors and are the positive supply for the high-side gate drives. The bootstrap capacitors are charged to approximately VREG when the associated output Sx terminal is low. When the Sx output swings high, the charge on the bootstrap capacitor causes the voltage at the corresponding Cx terminal to rise with the output to provide the boosted gate voltage needed for the high-side FETs. direction of load current (see table 1). The PHASE pin can also be used as a PWM input when full four-quadrant control (fast decay synchronous rectification) is required (see table 2). SR Pin This enables or disables synchronous rectification. When SR is high, synchronous rectification is enabled. When a PWMoff phase occurs (low on either or both of the PWMH and PWML Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 8 A3941 Automotive Full Bridge MOSFET Driver Table 1. Phase Control Truth Table Inputs PWMH 1 1 0 1 0 0 1 1 0 PWML 1 1 1 0 1 1 0 0 0 PHASE 1 0 X X 1 0 1 0 X SR X X 1 1 0 0 0 0 X HA H L L H L L H L L LA L H H L L H L L L HB L H L H L L L H L LB H L H L H L L L L Ouputs SA HS LS LS HS Z LS HS Z Z SB LS HS LS HS LS Z Z HS Z Mode of Operation Bridge driven with A high and B low Bridge driven with B high and A low Slow decay, both low-side drivers on or low-side brake Slow decay, both high-side drivers on or high-side brake Slow decay, current flow A to B, low-side diode rectification Slow decay, current flow B to A, low-side diode rectification Slow decay, current flow A to B, high-side diode rectification Slow decay, current flow B to A, high-side diode rectification Fast decay, diode rectification or coast X = don't care (same for input 1 or input 0), HS = high-side FET active, LS = low-side FET active, Z = high impedance, both FETs off Table 2. PWM Options Inputsa SR X 0 1 1 0 0 X aX bPWM PWM Effectb PHASE PWM 1 0 1 0 1 0 1 0 1 0 X 100% A to B A to B B to A A to B B to A A to B B to A A to B B to A A to B B to A Coast 0% B to A Coast Brake Brake Brakec Brakec Coast 1 PWMH 1 PWM PWM 1 PWM 1 0 PWML Decay Fast Fast Slow Slow Slow Slow Fast Mode of Operation Full four-quadrant control, zero average load current at 50% PWM Fast decay, diode recirculation or coast High-side PWM, low-side MOSFET recirculation Low-side PWM, high-side MOSFET recirculation High-side PWM, low-side diode recirculation Low-side PWM, high-side diode recirculation Coast, all MOSFETs off PWM 1 PWM 1 PWM 0 indicates don't care condition. The action is the same for input 1 or input 0. Effect indicates the effect on the load current direction or the equivalent action. cWith SR disabled, braking is only effective in one direction when sufficient forward voltage is available to allow the diode to conduct. Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 9 A3941 Automotive Full Bridge MOSFET Driver pins), synchronous rectification turns on the MOSFET that is complementary to the one that is turned off. This ensures that the current passes through the lower resistance MOSFET rather than the diode. When SR is low, synchronous rectification is disabled. In this case, fewer MOSFET switching cycles occur, reducing dissipation in the A3941. However, load current recirculates through the higher resistance body diode of the power MOSFETs, causing greater power dissipation in the power bridge. RESET Pin This is an active-low input, and when active it allows the A3941 to enter sleep mode. When RESET is held low, the regulator and all internal circuitry are disabled and the A3941 enters sleep mode. Before fully entering sleep mode, there is a short delay while the regulator decoupling and storage capacitors discharge. This typically takes a few milliseconds, depending on the application conditions and component values. During sleep mode, current consumption from the VBB supply is reduced to a minimal level. In addition, latched faults and the corresponding fault flags are cleared. When the A3941 is coming out of sleep mode, the protection logic ensures that the gate drive outputs are off until the charge pump reaches its correct operating condition. The charge pump stabilizes in approximately 3 ms under nominal conditions. RESET can be used also to clear latched fault flags without entering sleep mode. To do so, hold RESET low for less then the reset pulse time, tRES. This clears any latched fault that disables the outputs, such as short circuit detection or bootstrap capacitor undervoltage. Note that the A3941 can be configured to start without any external logic input. To do so, pull up the RESET pin to VBB by means of an external resistor. The resistor value should be between 20 and 33 k. Several brake states are possible using combinations of inputs on PWMH, PWML, and SR. For example, holding PWML and SR high, while PWMH is low, turns on both low-side FETs to short the load. The shorting path is always present and provides braking in both directions of motor rotation. Another example is holding SR low, when PWML is high and PWMH is low, making only one low-side FET active, and the braking current flow through the body diode of the opposite low-side FET. This provides braking in only one direction, because the diode does not permit the braking current to flow if the motor is reversed. Also, the braking current can be made to circulate around the high-side switches by swapping PWMH and PWML. Diagnostics Several diagnostic features are integrated into the A3941 to provide indication of fault conditions and, if required, take action to prevent permanent damage. In addition to system-wide faults such as undervoltage and overtemperature, the A3941 integrates individual drain-source monitors for each external FET, to provide short circuit detection. Diagnostic Management Pins VDSTH Pin Faults on the external FETs are determined by measuring the drain-source voltage, VDS , of each active FET and comparing it to the threshold voltage applied to the VDSTH input, VDSTH. To avoid false fault detection during switching transients, the comparison is delayed by an internal blanking timer. If the voltage applied to the VDSTH pin is greater than the disable threshold voltage, VDSDIS , then FET short circuit detection is disabled. VDRAIN Pin This is a low current sense input from the top of the Coast and Brake States To put the power bridge into a coast state, that is all power bridge MOSFETs switched off, the two PWM inputs, PWMH and PWML, must be held low and at the same time SR must be held low. This forces all gate drive outputs low. Braking is achieved by forcing the power bridge to apply a short across the load, allowing the back EMF of the load to generate a braking torque. external FET bridge. This input allows accurate measurement of the voltage at the drain of the high-side FETs. It should be connected directly to the common connection point for the drains of the power bridge FETs at the positive supply connection point. The input current to the VDRAIN pin is proportional to the voltage on the VDSTH pin and can be approximated by: IVDRAIN = 72 x VDSTH + 52 , where IVDRAIN is the current into the VDRAIN pin, in A, and VDSTH is the voltage on the VDSTH pin, in V. FF1 and FF2 Pins These are open drain output fault flags, which indicate fault conditions by their state, as shown in table 3. In Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 10 A3941 Automotive Full Bridge MOSFET Driver the event that two or more faults are detected simultaneously, the state of the fault flags will be determined by a logical OR of the flag states for all detected faults. Table 3. Fault Definitions Flag State FF1 Low Low Low Low High High High High FF2 Low High High High Low High High High Fault Description No fault Short-to-ground Short-to-supply Shorted load Overtemperature V5 undervoltage VREG undervoltage Bootstrap undervoltage Disable Outputs* No Yes Yes Yes No Yes Yes Yes Fault Latched - Yes Yes Yes No No No Yes Bootstrap Capacitor Undervoltage The A3941 monitors the voltage across the individual bootstrap capacitors to ensure they have sufficient charge to supply the current pulse for the highside drive. Before a high-side drive can be turned on, the voltage across the associated bootstrap capacitor must be higher than the turn-on voltage limit. If this is not the case, then the A3941 will start a bootstrap charge cycle by activating the complementary low-side drive. Under normal circumstances, this will charge the bootstrap capacitor above the turn-on voltage in a few microseconds and the high-side drive will then be enabled. The bootstrap voltage monitor remains active while the high-side drive is active and, if the voltage drops below the turn-off voltage, a charge cycle is initiated. In either case, if there is a fault that prevents the bootstrap capacitor charging, then the charge cycle will timeout, the fault flags (indicating an undervoltage) will be set, and the outputs will be disabled. The bootstrap undervoltage fault state remains latched until RESET is set low. V5 Undervoltage The output of the logic supply regulator volt- *Yes indicates all gate drives low, and all FETs off. Fault States Overtemperature If the junction temperature exceeds the over- temperature threshold, typically 165C, the A3941 will enter the overtemperature fault state and FF1 will go high. The overtemperature fault state, and FF1, will only be cleared when the temperature drops below the recovery level defined by TJF - TJFhys . No circuitry will be disabled. External control circuits must take action to limit the power dissipation in some way so as to prevent overtemperature damage to the A3941 chip and unpredictable device operation. VREG Undervoltage VREG supplies the low-side gate driver and the bootstrap charge current. It is critical to ensure that the voltages are sufficiently high before enabling any of the outputs. If the voltage at VREG, VREG , drops below the falling VREG undervoltage lockout threshold, VREGUVoff , then the A3941 will enter the VREG undervoltage fault state. In this fault state, both FF1 and FF2 will be high, and the outputs will be disabled. The VREG undervoltage fault state and the fault flags will be cleared when VREG rises above the rising VREG undervoltage lockout threshold, VREGUVon. The VREG undervoltage monitor circuit is active during power-up, and the A3941 remains in the VREG undervoltage fault state until VREG is greater than the rising VREG undervoltage lockout threshold, VREGUVon. age at V5 is monitored to ensure correct logical operation. If the voltage at V5, V5 , drops below the falling V5 undervoltage lockout threshold, V5UVoff , then the A3941 will enter the V5 undervoltage fault state. In this fault state, both FF1 and FF2 will be high, and the outputs will be disabled. In addition, because the state of other reported faults cannot be guaranteed, all fault states and fault flags are reset and replaced by the fault flags corresponding to a V5 undervoltage fault state. For example, a V5 undervoltage will reset an existing short circuit fault condition and replace it with a V5 undervoltage fault. The V5 undervoltage fault state and the fault flags will be cleared when V5 rises above the rising V5 undervoltage lockout threshold defined by V5UVoff + V5UVhys. The V5 undervoltage monitor circuit is active during power-up, and the A3941 remains in the V5 undervoltage fault state until V5 is greater than the rising VREG undervoltage lockout threshold, V5UVoff +V5UVhys. Short Fault Operation Shorts in the power bridge are determined by monitoring the drain-souce voltage, VDS , of each active FET and comparing it to the fault threshold voltage at the VDSTH pin. Because power MOSFETs take a finite time to reach the rated on-resistance, the measured drain-source voltages will show a fault as the phase switches. To avoid such false short fault detec- Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 11 A3941 Automotive Full Bridge MOSFET Driver tions, the output from the comparators are ignored under two conditions: while the external FET is off, and until the end of the period, referred to as the fault blank time, after the FET is turned on. When the FET is turned on, if the drain-source voltage exceeds the voltage at the VDSTH pin at any time after the fault blank time, then a short fault will be detected. This fault will be latched and the FET disabled until reset. In applications where short detection is not required, this feature may be disabled by connecting VDSTH to V5 or by applying a voltage greater than the disable threshold voltage, VDSDIS . This completely disables the VDS monitor circuits, preventing detection of short faults and any indication of short faults by the fault flags. In this condition the external FETs will not be protected by the A3941. Short to Supply When VDSTH is less than the disable threshold The result of this comparison is ignored if the FET is not active. It also is ignored for one fault blank time interval after the FET is turned on. If, when the comparator is not being ignored, its output indicates that VDS exceeds the voltage at the VDSTH pin, then FF2 will be high. Short to Ground When VDSTH is less than the disable threshold voltage, VDSDIS , a short from any of the motor phase connections to ground is detected by monitoring the voltage across the high-side FETs in each phase, using the appropriate Sx pin and the voltage at VDRAIN. This drain-source voltage, VDS , is continuously compared to the voltage on the VDSTH pin. The result of this comparison is ignored if the FET is not active. It also is ignored for one fault blank time interval after the FET is turned on. If, when the comparator is not being ignored, its output indicates that VDS exceeds the voltage at the VDSTH pin, FF2 will be high. Shorted Load The short-to-ground and short-to-supply monitor circuits will also detect a short across a motor phase winding. In most cases, a shorted winding will be indicated by a high-side and low-side fault being detected at the same time. In some cases the relative impedances may permit only one of the shorts to be detected. voltage, VDSDIS, a short from any of the motor phase connections to the battery or VBB connection is detected by monitoring the voltage across the low-side FETs in each phase, using the appropriate Sx pin and the LSS pin. This drain-source voltage, VDS, is continuously compared to the voltage on the VDSTH pin. Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 12 A3941 Automotive Full Bridge MOSFET Driver Applications Information Power Bridge Management Using PWM Control The A3941 provides two PWM control signals, a phase control for current direction, and the ability to enable or disable synchronous rectification. This allows a wide variety of full bridge control schemes to be implemented. The six basic schemes are shown in table 2 and described further below. Slow Decay Slow decay is the simplest and most common GHA LOAD GHB GHA LOAD GHB GLA GLB Driving Outputs 1 Phase A B 1 1 0 GHx GLx H L L H GLA GLB Inputs PWMH PWML PHASE SR control configuration. Figure 1A shows the path of the bridge and load current when a PWM signal is applied to PWMH, with PWML and PHASE tied high, and SR low. In this case the high-side MOSFETs are switched off during the current decay time (PWM off-time) and load current recirculates through the low-side MOSFETs. This is commonly referred to as high-side chopping or high-side PWM. The recirculating current flows through the body diode of the low-side MOSFET, which is complementary to the high-side MOSFET being switched off. Improved efficiency can be achieved by turning on the complementary MOSFETs during the PWM off-time to short the reverse diode and provide synchronous rectification. This can be easily achieved by taking SR high as shown in figure 1B. By applying the PWM signal to the PWML pin instead of the PWMH pin, the low-side MOSFET is turned off during the PWM off-time and the load current recirculates through the high-side MOSFETs as in figure 1C. In the three slow decay configurations shown, the direction of the average current in the load can be reversed by simply applying a low level to the PHASE pin. Referring to the slow decay entries in table 2, when PHASE is high the average current flows from the phase A connection (SA) to the phase B connection (SB). When PHASE is low the direction is from B to A. Fast Decay While slow decay usually provides sufficient control over the load current for most simple control systems, it is possible that current control stability can be affected by, for example, the back EMF of the load. In these cases, typically actuator positioning or servo control systems, it may be necessary to use fast decay to provide continuous control over the load current. The A3941 can be configured to provide fast decay using either diode recirculation or synchronous rectification. Recirculating Inputs Outputs 0 Phase A B PWMH PWML PHASE SR 1 1 0 GHx GLx H L L H (A) Slow decay, diode recirculation, high-side PWM GHA LOAD GHB GHA LOAD GHB GLA GLB Driving Outputs 1 Phase A B 1 1 1 GHx GLx H L L H GLA GLB Inputs PWMH PWML PHASE SR Recirculating Inputs Outputs 0 Phase A B PWMH PWML PHASE SR 1 1 1 GHx GLx L H L H (B) Slow decay, SR active, high-side PWM GHA LOAD GHB GHA LOAD GHB GLA GLB Driving Outputs 1 Phase A B 1 1 1 GHx GLx H L L H GLA GLB Inputs PWMH PWML PHASE SR Recirculating Inputs Outputs 1 Phase A B PWMH PWML PHASE SR 0 1 1 GHx GLx H L H L Fast decay with diode recirculation is achieved by applying a PWM signal at the same time to both PWM inputs, PWMH and PWML, with SR disabled (figure 2A). Because current recirculation is through the body diodes of the MOSFETs, the average load current cannot be negative so, as for the slow decay (C) Slow decay, SR active, low-side PWM Figure 1. Slow decay power bridge current paths Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 13 A3941 Automotive Full Bridge MOSFET Driver schemes, the PHASE input is still required to reverse the load current. Although fast decay with diode rectification provides a higher degree of current control than slow decay schemes, it still may not provide sufficient control for servo systems where full fourquadrant control is required. This is only possible using fast decay with synchronous rectification. By applying the PWM signal to the PHASE input, and holding PWMH and PWML and SR high (figure 2B), the load current can be controlled in both directions with a single PWM signal. Because all four MOSFETs in the bridge change state, the supply can be directly applied to the load in either direction. The effect is: when the PWM duty cycle is less than 50%, the average current flows from B to A; when greater than 50%, the average current flows from A to B; and when at 50%, the average current is zero. This allows the load current to be independent of any back EMF voltage generated, for example by a rotating motor, and effectively allowing the applied torque to work with or against a motor in either direction. Synchronous Rectification Synchronous rectification is used to GHA LOAD GHB GHA LOAD GHB GLA GLB Driving Outputs 1 Phase A B 1 1 0 GHx GLx H L L H GLA GLB Inputs PWMH PWML PHASE SR Recirculating Inputs Outputs 0 Phase A B PWMH PWML PHASE SR 0 1 0 GHx GLx L L L L (A) Fast decay, diode recirculation GHA LOAD GHB GHA LOAD GHB GLA GLB Driving Outputs 1 Phase A B 1 1 1 GHx GLx H L L H GLA GLB Inputs reduce power dissipation in the external MOSFETs. As described above, the A3941 can be instructed to turn on the appropriate low-side and high-side driver during the load current recirculation PWM off-cycle. During the decay time, synchronous rectification allows current to flow through the selected MOSFET, rather than through the source-drain body diode. The body diodes of the recirculating power MOSFETs will conduct only during the dead time that occurs at each PWM transition. PWMH PWML PHASE SR Recirculating Inputs Outputs 1 Phase A B PWMH PWML PHASE SR 1 0 1 GHx GLx L H H L (B) Fast decay, SR active, full four-quadrant control Figure 2. Fast decay power bridge current paths 4.5 4.0 3.5 Dead Time t DEAD (s) 3.0 2.5 2.0 1.5 1.0 0.5 0 0 50 100 150 200 250 300 RDEAD (k) 350 400 450 To prevent cross-conduction (shoot through) in any phase of the power FET bridge, it is necessary to have a dead time delay, tDEAD , between a high-side or low-side turn-off and the next complementary turn-on event. The potential for cross-conduction occurs when any complementary high-side and low-side pair of FETs are switched at the same time; for example, when using synchronous rectification or after a bootstrap capacitor charging cycle. In the A3941, the dead time for both phases is set by a single dead-time resistor, RDEAD , between the RDEAD and AGND pins. Figure 3. Dead time versus RDEAD , (full range) Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 14 A3941 Automotive Full Bridge MOSFET Driver For RDEAD values between 3 k and 240 k, at 25C the nominal value of tDEAD in ns can be approximated by: 7200 , (1) tDEAD(nom) = 50 + 1.2 + (200 / RDEAD) where RDEAD is in k. Greatest accuracy is obtained for values of RDEAD between 6 and 60 k, which are shown in figure 3. The IDEAD current can be estimated by: 1.2 IDEAD = RDEAD PWML=0). This effectively short-circuits the back EMF of the motor, creating a breaking torque. During braking, the load current can be approximated by: VBEMF IBRAKE = , RL (3) where VBEMF is the voltage generated by the motor and RL is the resistance of the phase winding. Care must be taken during braking to ensure that maximum ratings of the power FETs are not exceeded. Dynamic braking is equivalent to slow decay with synchronous rectification. . (2) The maximum dead time, 6 s typical, can be set by connecting the RDEAD pin directly to the V5 pin. The choice of power FET and external series gate resistance determine the selection of the dead-time resistor, RDEAD. The dead time should be long enough to ensure that one FET in a phase has stopped conducting before the complementary FET starts conducting. This should also take into account the tolerance and variation of the FET gate capacitance, the series gate resistance, and the on-resistance of the A3941 internal drives. Dead time will be present only if the on-command for one FET occurs within tDEAD after the off-command for its complementary FET. In the case where one side of a phase drive is permanently off, for example when using diode rectification with slow decay, then the dead time will not occur. In this case the gate drive will turn on within the specified propagation delay after the corresponding phase input goes high. (Refer to the Gate Drive Timing diagrams.) Bootstrap Capacitor Selection The bootstrap capacitors, CBOOTx, must be correctly selected to ensure proper operation of the A3941. If the capacitances are too high, time will be wasted charging the capacitor, resulting in a limit on the maximum duty cycle and the PWM frequency. If the capacitances are too low, there can be a large voltage drop at the time the charge is transferred from CBOOTx to the FET gate, due to charge sharing. To keep this voltage drop small, the charge in the bootstrap capacitor, QBOOT, should be much larger than the charge required by the gate of the FET, QGATE. A factor of 20 is a reasonable value, and the following formula can be used to calculate the value for CBOOT : QBOOT = CBOOT x VBOOT = QGATE x 20 , Fault Blank Time To avoid false short fault detection, the output from the VDS monitor for any FET is ignored when that FET is off and for a period of time after it is turned on. This period of time is the fault blank time. Its length is the dead time, tDEAD , plus an additional period of time that compensates for the delay in the VDS monitors. This additional delay is typically 300 to 600 ns. therefore: CBOOT = QGATE x 20 VBOOT , (4) where VBOOT is the voltage across the bootstrap capacitor. The voltage drop across the bootstrap capacitor as the FET is being turned on, V , can be approximated by: V QGATE CBOOT . (5) Braking The A3941 can be used to perform dynamic braking either by forcing all low-side FETs on and all high-side FETs off (SR=1, PWMH=0, and PWML=1) or conversely by forcing all lowside FETs off and all high-side FETs on (SR=1, PWMH=1, and So, for a factor of 20, V would be approximately 5% of VBOOT . The maximum voltage across the bootstrap capacitor under normal operating conditions is VREG(max). However, in some circumstances the voltage may transiently reach 18 V, the clamp Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 15 A3941 Automotive Full Bridge MOSFET Driver voltage of the Zener diodes between the Cx and Sx pins. In most applications, with a good ceramic capacitor the working voltage can be limited to 16 V. Bootstrap Charging It is good practice to ensure the high-side bootstrap capacitor is completely charged before a high-side PWM cycle is requested. The time required to charge the capacitor, tCHARGE (s), is approximated by: tCHARGE = CBOOT x V 100 , (6) capacitors. When a low-side FET is turned on, the gate-drive circuit will provide the high transient current to the gate that is necessary to turn on the FET quickly. This current, which can be several hundred milliamperes, cannot be provided directly by the limited output of the VREG regulator, and must be supplied by an external capacitor connected to VREG. The turn-on current for the high-side FET is similar in value to that for the low-side FET, but is mainly supplied by the bootstrap capacitor. However the bootstrap capacitor must then be recharged from the VREG regulator output. Unfortunately the bootstrap recharge can occur a very short time after the lowside turn-on occurs. This requires that the value of the capacitor connected between VREG and AGND should be high enough to minimize the transient voltage drop on VREG for the combination of a low-side FET turn-on and a bootstrap capacitor recharge. A value of 20 x CBOOT is a reasonable value. The maximum working voltage will never exceed VREG , so the capacitor can be rated as low as 15 V. This capacitor should be placed as close as possible to the VREG pin. where CBOOT is the value of the bootstrap capacitor, in nF, and V is the required voltage of the bootstrap capacitor. At power-up and when the drives have been disabled for a long time, the bootstrap capacitor can be completely discharged. In this case V can be considered to be the full high-side drive voltage, 12 V. Otherwise, V is the amount of voltage dropped during the charge transfer, which should be 400 mV or less. The capacitor is charged whenever the Sx pin is pulled low and current flows from VREG through the internal bootstrap diode circuit to CBOOT. Bootstrap Charge Management The A3941 provides automatic bootstrap capacitor charge management. The bootstrap capacitor voltage for each phase is continuously checked to ensure that it is above the bootstrap under-voltage threshold, VBOOTUV. If the bootstrap capacitor voltage drops below this threshold, the A3941 will turn on the necessary low-side FET, and continue charging until the bootstrap capacitor exceeds the undervoltage threshold plus the hysteresis, VBOOTUV + VBOOTUVhys. The minimum charge time is typically 7 s, but may be longer for very large values of bootstrap capacitor (>1000 nF). If the bootstrap capacitor voltage does not reach the threshold within approximately 200 s, an undervoltage fault will be flagged. Supply Decoupling Because this is a switching circuit, there are current spikes from all supplies at the switching points. As with all such circuits, the power supply connections should be decoupled with a ceramic capacitor, typically 100 nF, between the supply pin and ground. These capacitors should be connected as close as possible to the device supply pins VBB and V5, and the ground pin, GND. Power Dissipation In applications where a high ambient temperature is expected, the on-chip power dissipation may become a critical factor. Careful attention should be paid to ensure the operating conditions allow the A3941 to remain in a safe range of junction temperature. The power consumed by the A3941, PD, can be estimated by: PD = PBIAS + PCPUMP + PSWITCHING , given: PBIAS = VBB x IBB ; (8) (7) VREG Capacitor Selection The internal reference, VREG, supplies current for the low-side gate drive circuits and the charging current for the bootstrap Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 16 A3941 Automotive Full Bridge MOSFET Driver PCPUMP = [( 2 VBB) - VREG] IAV or = [VBB - VREG] IAV where: IAV = QGATE x N x fPWM , , for VBB < 15 V, , for VBB 15 V, (9) (10) PSWITCHING = QGATE x VREG x N x fPWM x Ratio ; N is the number of FETs switching during a PWM cycle, and 10 . Ratio = RGATE + 10 N = 1 for slow decay with diode recirculation, N = 2 for slow decay with synchronous rectification or for fast decay with diode recirculation, and N = 4 for fast decay with synchronous rectification. Layout Recommendations Careful consideration must be given to PCB layout when designing high frequency, fast switching, high current circuits. The following are recommendations regarding some of these considerations: * The A3941 ground, GND, and the high-current return of the external FETs should return separately to the negative side of the motor supply filtering capacitor. This will minimize the effect of switching noise on the device logic and analog reference. * The exposed thermal pad should be connected to the GND pin and may form part of the Controller Supply ground (see figure 4). * Minimize stray inductance by using short, wide copper traces at the drain and source terminals of all power FETs. This includes motor lead connections, the input power bus, and the common source of the low-side power FETs. This will minimize voltages induced by fast switching of large load currents. * Consider the use of small (100 nF) ceramic decoupling capacitors across the sources and drains of the power FETs to limit fast transient voltage spikes caused by the inductance of the circuit trace. * Keep the gate discharge return connections Sx and LSS as short as possible. Any inductance on these traces will cause negative transitions on the corresponding A3941 pins, which may exceed the absolute maximum ratings. If this is likely, consider the use of clamping diodes to limit the negative excursion on these pins with respect to GND. * Sensitive connections such as RDEAD and VDSTH, which have very little ground current, should be connected to the Quiet ground (refer to figure 4), which is connected independently, closest to the GND pin. These sensitive components should never be connected directly to the supply common or to a common ground plane. They must be referenced directly to the GND pin. * The supply decoupling for VBB, VREG, and V5 should be connected to the Controller Supply ground, which is independently connected close to the GND pin. The decoupling capacitors should also be connected as close as practicable to the relevant supply pin. * If layout space is limited, then the Quiet and Controller Supply grounds may be combined. In this case, ensure that the ground return of the dead time resistor is close to the GND pin. * Check the peak voltage excursion of the transients on the LSS pin with reference to the GND pin, using a close grounded (tip and barrel) probe. If the voltage at LSS exceeds the absolute maximum shown in this datasheet, add either or both of additional clamping and capacitance between the LSS pin and the GND pin, as shown in figure 4. * Gate charge drive paths and gate discharge return paths may carry a large transient current pulse. Therefore, the traces from GHx, GLx, Sx, and LSS should be as short as possible to reduce the circuit trace inductance. * Provide an independent connection from LSS to the common point of the power bridge. It is not recommended to connect LSS directly to the GND pin, as this may inject noise into sensitive functions such as the timer for dead time. * A low-cost diode can be placed in the connection to VBB to provide reverse battery protection. In reverse battery conditions, it is possible to use the body diodes of the power FETs to clamp the reverse voltage to approximately 4 V. In this case, the additional diode in the VBB connection will prevent damage to the A3941 and the VDRAIN input will survive the reverse voltage. Note that the above are only recommendations. Each application is different and may encounter different sensitivities. A driver running a few amps will be less susceptible than one running with 150 A, and each design should be tested at the maximum current to ensure any parasitic effects are eliminated. Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 17 A3941 Automotive Full Bridge MOSFET Driver Optional reverse battery protection VBB VDRAIN VREG GHB GHA + Supply A3941 VS SA SB Motor GLA VDSTH RDEAD GND GLB LSS RS Optional components to limit LSS transients Quiet Ground Controller Supply Ground Power Ground Supply Common Figure 4. Supply routing suggestions Input and Output Structures CP1 CP2 VDRAIN VBB VS VBB 20 V 18 V Cx 18 V 19 V GHx 18 V Sx VREG 18 V 18 V 19 V 18 V 20 V 6V ESD (B) Supply protection structures ESD 18 V GLx 10 FFx LSS 6V RESET 50 k 6V 3 k (A) Gate drive outputs ESD (C) Fault output ESD (D) RESET input ESD 1.2 V PWMx SR PHASE 3 k VDSTH 1 k RDEAD 100 8.5 V 8.5 V 8.5 V (E) Logic inputs, no pulldown (F) VDS monitor threshold input (G) RDEAD Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 18 A3941 Automotive Full Bridge MOSFET Driver Pin-out Diagram VDRAIN LSS GLB SB GHB CB VREG VREG CA GHA SA GLA VBB VBB 1 2 3 4 5 6 Control Logic 28 tDEAD 27 26 25 24 23 22 21 Reg 20 19 18 17 Charge Pump 16 15 VDSTH RDEAD FF2 FF1 RESET PWMH PWML SR V5 PHASE GND GND CP1 CP2 7 8 9 10 11 12 13 14 Reg Terminal List Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Name VDRAIN LSS GLB SB GHB CB VREG VREG CA GHA SA GLA VBB VBB CP2 Description High-side common drain Low-side common source Low-side gate drive B Load connection B High-side gate drive B Bootstrap capacitor B Regulated 13 V Regulated 13 V Bootstrap capacitor A High-side gate drive A Load connection A Low-side gate drive A Main supply Main supply Pump capacitor Number 16 17 18 19 20 21 22 23 24 25 26 27 28 - Name CP1 GND GND PHASE V5 SR PWML PWMH RESET FF1 FF2 RDEAD VDSTH PAD Ground Ground Phase control input 5 V regulator SR control input Low-side PWM control input High-side PWM control input Reset input Fault Flag 1 output Fault Flag 2 output Dead time setting input VDS threshold level Input Exposed pad for enhanced thermal dissipation (underside) Description Pump capacitor Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 19 A3941 Automotive Full Bridge MOSFET Driver Package LP 28-Pin TSSOP with Exposed Thermal Pad 9.70 0.10 28 4 4 +0.05 0.15 -0.06 1.65 28 0.45 0.65 B 3.00 A 4.40 0.10 6.40 0.20 0.60 0.15 (1.00) 3.00 6.10 1 2 5.00 0.25 SEATING PLANE 0.65 1.20 MAX 0.10 MAX For reference only (reference JEDEC MO-153 AET) Dimensions in millimeters Dimensions exclusive of mold flash, gate burrs, and dambar protrusions Exact case and lead configuration at supplier discretion within limits shown A Terminal #1 mark area B Exposed thermal pad (bottom surface) C Reference land pattern layout (reference IPC7351 SOP65P640X120-29CM); All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and PCB layout tolerances; when mounting on a multilayer PCB, thermal vias at the exposed thermal pad land can improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5) C SEATING PLANE GAUGE PLANE 12 5.00 C PCB Layout Reference View 28X 0.10 C +0.05 0.25 -0.06 Copyright (c)2008, Allegro MicroSystems, Inc. The products described here are manufactured under one or more U.S. patents or U.S. patents pending. Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro's products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the failure of that life support device or system, or to affect the safety or effectiveness of that device or system. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use. For the latest version of this document, visit our website: www.allegromicro.com Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 20 |
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